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source code for TB3186 (loading code to TCM)
http://ww1.microchip.com/downloa... explains it, but the code sample is an image in the document.  Does anyone have an example - ideally for ATSAMD5x - as an editable file?...
Wed. Oct 24, 2018 - 01:29 PM
Atmel Studio, START - reconfigure MCU from SAMD51 to SAME54???
I swear the easier developers try to make a tool to use, the harder it is to do some things... Is this even possible?
Mon. Oct 15, 2018 - 07:44 PM
Feeling inept with SAME54 eval and trivial UART...
32KHz ext osc --> 120 MHz MCU and 96MHz clock for UART.  Intention was to test fastest reasonable on-board serial lines, hence the name.  96MHz clock divided as GCLK2...
Fri. Oct 12, 2018 - 01:21 PM
has anyone here tried C# on a SAMD5x?
For the life of me, I wouldn't do it, but I have been asked.  I see general references to dot-net for core M4, so perhaps it is possible.  I'd want to do the working...
Sat. Sep 8, 2018 - 04:40 PM
ATSAMD51 - load code segments to sram at boot?
I will have some tight loops that really need to be sped up.  Similar code in a TMS320C2809 had to be loaded to sram for execution to avoid the wait states.  Is there a...
Tue. Aug 28, 2018 - 11:56 AM
(solved while posting) ATSAMD51 counter, 32bit, retrieving the count??
Pretty simply, the CPU clock (GCLK0) really is running 120MHz. The first function is doing what it claims - OK, taking it on faith that it counts, but it is clocked from a valid...
Sat. Aug 4, 2018 - 08:48 PM
ATSAMD51 ADC Errata clarification
1.1.2 ADC The ADC TUE/INL/DNL performance is not guaranteed in the following scenarios: • Sampling frequency is above 500 ksps • ADC VREF is different from VDDANA Workaround None...
Mon. Jul 23, 2018 - 07:10 PM
ATSAMD51 NVM questions
I am sure I looked right at it, but for the life of me...  I need to roll my own bootloader (integrated into an app that we already have for loading hex files to dsPIC33 and...
Wed. Jul 18, 2018 - 05:54 PM
question about xxx.INTENSET.bit.yyy
I have code that uses various interrupts that are enabled and disabled on the fly.  At some point this week it seems like, for example, SERCOM3->USART.INTENCLR.bit.DRE = 1...
Mon. May 7, 2018 - 02:21 AM
EVSYS issue ATSAMD51
As an offshoot to my ADC timing issue, tech support discussion migrated from polling TC0 to EVSYS.  Sounds like a great idea, except something is amiss.   I set up the...
Fri. Apr 20, 2018 - 11:05 AM
ATSAMD51 ADC timing not as expected.
32KHz external clock --> 120MHz DPLL0 --> CPU and /4 --> ADC source GCLK=30MHz.  ADC is set to use zero prescale (15MHz ADC clock)  in one shot mode.  This...
Wed. Apr 18, 2018 - 02:12 AM
["solved"] ATSAMD51 DAC at close to 1MSa/s timing frustration
I have 32768 external --> DPLL0 --> 120MHz and -->DPLL1--> a variable frequency.  In this case, it is at its max, 199.994MHz.   DPLL0 drives MCLK and DPLL0/...
Sun. Apr 8, 2018 - 03:36 AM

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