Strange SAMR21 event system behaviour

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Hi, everybody. I have some troubles with SAMR21 event system... I hope that somebody can help me.

 

1. TC3 - NPWM mode clocked by ULP32KHZ generator, PER=110, CC0=108, TC3/WO[0] INVERTED and routed to PA18. I have proper signal on out pin. In addition CC1 = 109 and MCEO1=1 and on this compare match EVENT to AC START COMPARE must be generated, but nothing happend.

 

2 AC - CH=0, SINGLE=1, POS=3(PA07), NEG=5(VDDANA Scaler), INTSEL=2(FALLING EDGE). Output Event routed to TC5 (count on event). As was mentioned above, conversion is not starting on MC1 event of TC3, but only manually... BUT event is generated NOT on FALLING EDGE of COM0, but on HIGH LEVEL of COMP0 and end of conversion... :-(

 

In documentation: 

 

Bits 6:5 – INTSEL[1:0]: Interrupt Selection
These bits select the condition for comparator n to generate an interrupt or event. COMPCTRLn.INTSEL can be
written only while COMPCTRLn.ENABLE is zero.
These bits are not synchronized.

 

So according to previous, my AC events MUST be generated on FALLING EDGE!!!

 

I'm using Lightweight stack 1.2.1.

 

Here is initialisation code:

 

#define TCC0_EVENT_CHANNEL          0
#define TCC1_EVENT_CHANNEL          1
#define TCC2_EVENT_CHANNEL          2
#define TC3_TO_AC_EVENT_CHANNEL     3
#define AC_TO_TC5_EVENT_CHANNEL     4
#define TC3_TO_ADC_EVENT_CHANNEL    5

           PM->APBCMASK.reg |= PM_APBCMASK_TC3;

            TC3->COUNT8.CTRLA.bit.ENABLE = 0;
            while (TC3->COUNT8.STATUS.bit.SYNCBUSY) {}

            /* Change clock source for TC3 to ULP32kHz oscilator */
            GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(TC3_GCLK_ID) | GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(LOW_POWER_32K_GEN);

            TC3->COUNT8.CTRLA.bit.MODE = TC_CTRLA_MODE_COUNT8_Val;
            TC3->COUNT8.CTRLA.bit.RUNSTDBY = 1;
            TC3->COUNT8.CTRLA.bit.WAVEGEN = TC_CTRLA_WAVEGEN_NPWM_Val;
            TC3->COUNT8.PER.reg = 110;
            TC3->COUNT8.CC[0].reg = 108;
            TC3->COUNT8.CC[1].reg = 109;
            TC3->COUNT8.EVCTRL.bit.MCEO1 = 1;
            TC3->COUNT8.CTRLC.bit.INVEN0 = 1;
            TC3->COUNT8.DBGCTRL.bit.DBGRUN = 1;
            HAL_GPIO_REFLECT_OUT_GND_out();
            HAL_GPIO_REFLECT_OUT_GND_clr();
            HAL_GPIO_REFLECT_OUT_pmuxen();

            PORT->Group[HAL_GPIO_PORTA].PMUX[9].bit.PMUXE = PORT_PMUX_PMUXE_E_Val;

            /* Configure AC for single operation starting on input event from TC3 and generating event on
               falling output. */
            PM->APBCMASK.reg |= PM_APBCMASK_AC;
            GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(AC_GCLK_ID_DIG) | GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(0);
            GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(AC_GCLK_ID_ANA) | GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(LOW_POWER_32K_GEN);
            AC->CTRLA.bit.SWRST = 1;
            while (AC->STATUSB.bit.SYNCBUSY) {}
            AC->EVCTRL.reg = AC_EVCTRL_COMPEI0 | AC_EVCTRL_COMPEO0;
            AC->CTRLA.bit.RUNSTDBY = 1;
            AC->COMPCTRL[0].reg = AC_COMPCTRL_MUXPOS_PIN3 | AC_COMPCTRL_MUXNEG_VSCALE |
                                  AC_COMPCTRL_SINGLE | AC_COMPCTRL_SPEED_HIGH |  AC_COMPCTRL_INTSEL_FALLING;
            AC->SCALER[0].reg = ac_level;

            HAL_GPIO_PHOTO_SENSOR_pmuxen();
            PORT->Group[HAL_GPIO_PORTA].PMUX[3].bit.PMUXO = PORT_PMUX_PMUXO_B_Val;

            /* Configure and enable TC5 counter */
            PM->APBCMASK.reg |= PM_APBCMASK_TC5;

            GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(TC5_GCLK_ID) | GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(LOW_POWER_32K_GEN);

            TC5->COUNT8.CTRLA.bit.ENABLE = 0;
            while (TC5->COUNT8.STATUS.bit.SYNCBUSY) {}
            TC5->COUNT8.CTRLA.bit.MODE = TC_CTRLA_MODE_COUNT8_Val;
            TC5->COUNT8.CTRLA.bit.RUNSTDBY = 1;
            TC5->COUNT8.DBGCTRL.bit.DBGRUN = 1;
            TC5->COUNT8.EVCTRL.bit.TCEI = 1;
            TC5->COUNT8.EVCTRL.bit.EVACT = TC_EVCTRL_EVACT_COUNT_Val;
            TC5->COUNT8.EVCTRL.bit.OVFEO = 1;
            TC5->COUNT8.PER.reg = Sens_Parm.reflect_imp_per_minor_unit;

            /* Event path from Compare1 of TC3 to AC_Start0 */
            ATOMIC_SECTION_ENTER
            EVSYS->USER.reg = EVSYS_USER_USER(EVSYS_ID_USER_AC_SOC_0) | EVSYS_USER_CHANNEL(TC3_TO_AC_EVENT_CHANNEL+1);
            EVSYS->CHANNEL.reg = EVSYS_CHANNEL_CHANNEL(TC3_TO_AC_EVENT_CHANNEL) | EVSYS_CHANNEL_EVGEN(EVSYS_ID_GEN_TC3_MCX_1) |
                                 EVSYS_CHANNEL_PATH_ASYNCHRONOUS;
            ATOMIC_SECTION_LEAVE
            /* Event path from AC (falling edge of comparison) to TC5 (count event) */
            ATOMIC_SECTION_ENTER
            EVSYS->USER.reg = EVSYS_USER_USER(EVSYS_ID_USER_TC5_EVU) | EVSYS_USER_CHANNEL(AC_TO_TC5_EVENT_CHANNEL+1);
            EVSYS->CHANNEL.reg = EVSYS_CHANNEL_CHANNEL(AC_TO_TC5_EVENT_CHANNEL) | EVSYS_CHANNEL_EVGEN(EVSYS_ID_GEN_AC_COMP_0) |
                                 EVSYS_CHANNEL_PATH_ASYNCHRONOUS;
            ATOMIC_SECTION_LEAVE
            /* Event path from overflow of TC5 to TCC2 */
            ATOMIC_SECTION_ENTER
            EVSYS->USER.reg = EVSYS_USER_USER(EVSYS_ID_USER_TCC2_EV_0) | EVSYS_USER_CHANNEL(TCC2_EVENT_CHANNEL+1);          

            EVSYS->CHANNEL.reg = EVSYS_CHANNEL_CHANNEL(TCC2_EVENT_CHANNEL) | EVSYS_CHANNEL_EVGEN(EVSYS_ID_GEN_TC5_OVF) |
                                 EVSYS_CHANNEL_PATH_ASYNCHRONOUS;
            ATOMIC_SECTION_LEAVE
            AC->CTRLA.bit.ENABLE = 1;
            while (AC->STATUSB.bit.SYNCBUSY) {}
            AC->COMPCTRL[0].bit.ENABLE = 1;
            while (AC->STATUSB.bit.SYNCBUSY) {}
            TC3->COUNT8.CTRLA.bit.ENABLE = 1;
            TC5->COUNT8.CTRLA.bit.ENABLE = 1;
 

 

Last Edited: Fri. Dec 2, 2016 - 11:48 AM
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Hi, everybody!

There was NO troubles...

TC3->COUNT8.CC[1].reg = 108; solves all problems...

I think that AC was starting too late... At time when power on photo sensor was switched off...

By the way delay was 2 periods of 32 kHz

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And with INTSEL is all OK