SAMR21B18 DFLL Clock Source occasionally never becomes ready

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I'm programming the SAMR21B18 module with the APPS_SIMPLE_EXAMPLE_STAR ASF Project which is made specifically for this module. However, occasionally (~1/5 times) the program gets stuck waiting for the DFLL clock source to become ready in the while loop located in the following section of code:

 

	/* DFLL Enable (Open and Closed Loop) */
#if CONF_CLOCK_DFLL_ENABLE == true
	system_clock_source_enable(SYSTEM_CLOCK_SOURCE_DFLL);
	while(!system_clock_source_is_ready(SYSTEM_CLOCK_SOURCE_DFLL));
	if (CONF_CLOCK_DFLL_ON_DEMAND) {
		SYSCTRL->DFLLCTRL.bit.ONDEMAND = 1;
	}
#endif

The call stack is as follows:

system_init() -> system_clock_init() -> system_clock_source_is_ready()

 

I'm assuming I may have to reconfigure something within conf_clock.h even though the project was made specifically for this module, however, I don't know what this would be considering I don't see the issue the majority of the time. Any input is appreciated.