Hi,
I use attached an external RAM (ISI42S16160) to my SAME70 with the EBI interface. Here is my connections:
SAM RAM
16b data bus 16b data bus
A2:A11 A0:A9
SDA10 A10
A13:A14 A11:A12
other control signals ...
I can access the RAM in read / write mode correctly. But ...
from address 0 to 2^22 - 1, everything works fine,
from address 2^22 to 2^23 - 1, I read / write in the same data space as from 0 to 2^22 - 1,
from address 2^23 to 2^24 - 1, everything works fine,
from address 2^24 to 2^25 - 1, I read / write in the same data space as from 2^23 to 2^24 - 1,
etc...
I'm quite sure I badly connected my RAM to the µC, especialy the A10 pin of the RAM, but in the SAME70 datasheet I understood that the A10 pin has to be handled differently and needed to be connected to SDA10 pin of the µC. It's what is explain in the Schematic checklist (section 56-2-9) and it's what is given in the figure 56-4 (Schematic Example with a 16 Mb/16-bit SDRAM).
So did I connect my RAM wrongly? Or I missconfigured my RAM in the initialization process? Here is my initialization code:
/* Enable SMC peripheral clock */
pmc_enable_periph_clk(ID_SDRAMC);
/* SDRAM IS42S16100E configuration */
const sdramc_memory_dev_t sdram_issi_IS42S16160 = {
25, /* Block1 is at the bit 25, 2+9+13+1. */
0, /*
* This configures the SDRAM with the following parameters in the
*mode register:
* - bits 0 to 2: burst length: 1 (000b);
* - bit 3: burst type: sequential (0b);
* - bits 4 to 6: CAS latency;
* - bits 7 to 8: operating mode: standard operation (00b);
* - bit 9: write burst mode: programmed burst length (0b);
* - all other bits: reserved: 0b.
*/
{
SDRAMC_CR_NC_COL9 | /* 9 column bits. */
SDRAMC_CR_NR_ROW13 | /* 13 row bits (2K). */
SDRAMC_CR_NB_BANK2 | /* SDRAM 2 bank. */
SDRAMC_CR_CAS_LATENCY3 | /* CAS Latency 3. */
SDRAMC_CR_DBW | /* Data bus width 16 bits. */
SDRAMC_CR_TWR(5) | /* Write Recovery Delay. */
SDRAMC_CR_TRC_TRFC(13) | /* Row Cycle Delay and Row Refresh Cycle. */
SDRAMC_CR_TRP(5) | /* Row Precharge Delay. */
SDRAMC_CR_TRCD(5) | /* Row to Column Delay. */
SDRAMC_CR_TRAS(9) | /* Active to Precharge Delay. */
SDRAMC_CR_TXSR(15) /* Exit from Self Refresh to Active Delay. */
},
};
/* Complete SDRAM configuration */
sdramc_init((sdramc_memory_dev_t *)&sdram_issi_IS42S16160, sysclk_get_cpu_hz());
sdram_enable_unaligned_support();Thanks for any light