SAME70 Cache and USB

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I am using ASF3 and have a set up to use the SAME70 on an Xplained board. I am using the stdio_usb implementation to send and receive packetized messages over a virtual com port. The problem that I am having is that the USB misses the first part of a message. I finally looked back though old posts and found a note about the DCache and ICache. This was back at ASF V3.28, we are now at V3.49. I disabled the I and D caches and still missed bytes. I then modified init.c to include another routine that enabled and then disabled the I and D caches at initialization. Everything started working great. Does anyone have any in-site into what is causing this. The chip is ATSAME70Q21B using  ASF3.49.1, freeRTOS v10.0.0, and lwip v1.4.1. I realize that this is a cache coherency problem, and that I am using peripherals that utilize DMA transfers (as they should), but how can I identify where to utilize cache maintenance operations as the documentation is fuzzy at best on this. I need to identify if this is a problem in the ASF, the freeRTOS port, lwip, the actual silicon, or my base code.

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Sounds like a configuration problem. The ASF 3.49 driver for SAMx70's USBHS controller implements cache maintenance routines, but they're contingent on both UDD_EP_DMA_SUPPORTED and CONF_BOARD_ENABLE_CACHE_AT_INIT being defined. Have you verified that you have defined those pre-processor symbols?

 

Neither FreeRTOS nor LwIP will be affected by the existence of a cache on this device.

 

Steve

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