SAME54 Xplained Pro - DPLL with XOSC1 and Atmel Start

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#1
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Hi,

 

I try to get DPLL0/1 to run with XOSC1 (12 MHz). It seems Atmel Start does not calculate the Frequencies correctly.

 

Regarding to device DS, the DPLL Input freq must be < 3,4 MHz. When XOSC is selevted, it is divided by "2x(DIV+1)" (See DPLL Control B Register).

 

I Assume "Clock Divider" in Atmel Start should match that register bits. So set this to 5, would result in Divider of (2x(5+1) = 12).  Using XOSC1 as input (12 MHz) should result in 12 MHz/12 = 1 MHz -> the DPLL input frequency should be 1 MHz.

However, in Atmel Start the Clock Divider Setting does not change anything in the output frequency calculation. In the picture below the output frequency should be (99+1) * 1 MHz = 100 MHz.

It is shown as 1200 Mhz (presumably calculated from (99+1) * 12 MHz) however. Thus the Generate Code function refuses to generate the Project (Internal Server Error).

 

I did other tests using 12 MHz to drive a Genclk and feed back a divided down clock to DPLL. In that case code is generated but the software will do an infinite loop waiting for the PLL Lock bit.

 

Has anybody successful used Atmel Start + E54 DPLL with XOSC as source?

All examples for E54 seem to use 12 MHz directly or DPLL with 32kHz clock input.

 

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I used 32KHz, but you could run 12MHz through a GCLK /12 to get 1MHz and then feed that to DPLL.  I think you need to use GCLK3 to feed back to sources...

jeff

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jcandle wrote:

I used 32KHz, but you could run 12MHz through a GCLK /12 to get 1MHz and then feed that to DPLL.  I think you need to use GCLK3 to feed back to sources...

 

Thanks a lot! I tried it with GCLK3 (12 MHz / 12) and it works now. I tested it also with GCLK 2, works as well.

I was very sure to have tested the same weeks ago and it would stop in an infinite loop during PLL initialisation. Maybe I checked a wrong box before, or maybe Microchip exchanged some broken code meanwhile.

 

It should still work by using XOSC1 directly, but for me its totally fine this way.

 

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@jcandle: I think I have done the same as you with GCLK / 12, etc. but I get an infinite loop during PLL initialization.  Do you have any clues for me??

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@jcandle: I think I have done the same as you with GCLK / 12, etc. but I get an infinite loop during PLL initialization.  Do you have any clues for me??

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@mredd - I've had a hard time with this board and with Start (mostly Start).  I wrote raw code - taken from Start - for the 'D51 and found some eratta that were relevant.  Some of the status bits are non functional and interrupt flags are to be used.  I though that was in the 32Kext though and not the dpll.  

 

My clock code is posted in an older post (a year ago?).  

jeff

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I know this is an older post, but I wanted to add my feedback.  The OP is correct.  Atmel Start does not handle the clock divider going into either of the DPLLs properly.  Following is Figure 28-2 from the SAM-D5xE5x reference:

 

The clock divider (DPLLCTRLB.DIV) definitely occurs before the input to the DPLL.  This should allow either of the XOSCs to directly input into the DPLL without requiring use of an extra GCLK.  To verify this, I used the following code on my SAME54 Xplained board:

 

 

	// Run with a 12MHz external crystal on XOSC1
	OSCCTRL->XOSCCTRL[1].bit.ENALC      = 1;
	OSCCTRL->XOSCCTRL[1].bit.IMULT      = 4;
	OSCCTRL->XOSCCTRL[1].bit.IPTAT      = 3;
	OSCCTRL->XOSCCTRL[1].bit.ONDEMAND   = 0;
	OSCCTRL->XOSCCTRL[1].bit.XTALEN     = 1;
	OSCCTRL->XOSCCTRL[1].bit.ENABLE     = 1;
	// Wait for OSC to be ready
	while (0 == OSCCTRL->STATUS.bit.XOSCRDY1);

	// Set up DPLL0 to output 120MHz using XOSC1 output divided by 12 - max input to the PLL is 3.2MHz
	OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC  = 0;
	OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR      = 119;
	OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV      = 5; // 2 * (DIV + 1)
	OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK   = 3; // use XOSC1 clock reference
	OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = 0;
	OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE   = 1; // enable the PLL
	// Wait for PLL to be locked and ready
	while(0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK || 0 == OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY);

	// Connect DPLL0 to clock generator 0 (120MHz) - frequency used by CPU, AHB, APBA, APBB
	GCLK->GENCTRL[0].reg = GCLK_GENCTRL_SRC_DPLL0 | GCLK_GENCTRL_DIV(1) | GCLK_GENCTRL_GENEN;
        while (1 == GCLK->SYNCBUSY.bit.GENCTRL0);
	

 

I can confirm that this works perfectly on my board at 120MHz.

Last Edited: Fri. Oct 19, 2018 - 07:17 PM