AVR Freaks

That board has a 12MHz crystal, so you need to divide

the clock by four.  Using a timer to toggle an output

pin, you would have to configure it to count two clocks

only.  This will toggle at 6MHz yielding a 3MHz square

wave.

--Mike

    // Setup XOSC32K for external crystal oscillator 32768 Hz 
    REG_SYSCTRL_XOSC32K = SYSCTRL_XOSC32K_STARTUP(6) |	SYSCTRL_XOSC32K_XTALEN | SYSCTRL_XOSC32K_EN32K;
    REG_SYSCTRL_XOSC32K |= SYSCTRL_XOSC32K_ENABLE;
    while ((REG_SYSCTRL_PCLKSR & SYSCTRL_PCLKSR_XOSC32KRDY) == 0);

    // GCLK2 at 32768 Hz
    REG_GCLK_GENDIV = GCLK_GENDIV_ID(2) | GCLK_GENDIV_DIV(1);
    REG_GCLK_GENCTRL = GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_XOSC32K | GCLK_GENCTRL_ID(2);
    
    // Provide DFLL48M reference from GCLK2
    REG_GCLK_CLKCTRL = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN_GCLK2 | GCLK_CLKCTRL_ID_DFLL48;
    // Setup DFLL48M
    REG_SYSCTRL_DFLLCTRL = SYSCTRL_DFLLCTRL_ENABLE;
    while ((REG_SYSCTRL_PCLKSR & SYSCTRL_PCLKSR_DFLLRDY) == 0);
    REG_SYSCTRL_DFLLMUL = SYSCTRL_DFLLMUL_CSTEP(31) | SYSCTRL_DFLLMUL_FSTEP(511) | SYSCTRL_DFLLMUL_MUL(1464);
    REG_SYSCTRL_DFLLCTRL |= SYSCTRL_DFLLCTRL_MODE|SYSCTRL_DFLLCTRL_QLDIS;
    const uint32_t status = SYSCTRL_PCLKSR_DFLLLCKC | SYSCTRL_PCLKSR_DFLLLCKF;
    while((REG_SYSCTRL_PCLKSR & status) != status);
    while ((REG_SYSCTRL_PCLKSR & SYSCTRL_PCLKSR_DFLLRDY) == 0);	
    
    // Set wait state (1) for running the CPU at 48MHz
    REG_NVMCTRL_CTRLB = (1 << NVMCTRL_CTRLB_RWS_Pos);
    
    // Use DFLL48M for GCLK0 
    REG_GCLK_GENDIV = GCLK_GENDIV_ID(0) | GCLK_GENDIV_DIV(1);
    REG_GCLK_GENCTRL = GCLK_GENCTRL_OE | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL48M | GCLK_GENCTRL_ID(0);
    
    // Output GCLK0 48 MHz on PB14
    PORT->Group[1].PMUX[14/2].reg |= PORT_PMUX_PMUXE(MUX_PB14H_GCLK_IO0);
    PORT->Group[1].PINCFG[14].reg |= PORT_PINCFG_PMUXEN;

Is a start, this sets up a 48 MHz clock (you can skip the last part which outputs this clock to PB14).

With that you can generate a 3 MHz output in lots of ways as mentioned. Here is one way

    // GCLK1 also using DFLL48M but divide by 16 for 3 MHz
    REG_GCLK_GENDIV = GCLK_GENDIV_ID(1) | GCLK_GENDIV_DIV(16);
    REG_GCLK_GENCTRL = GCLK_GENCTRL_OE | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL48M | GCLK_GENCTRL_ID(1);		
    // Output GCLK1 on PA15
    PORT->Group[0].PMUX[15/2].reg |= PORT_PMUX_PMUXO(MUX_PA15H_GCLK_IO1);
    PORT->Group[0].PINCFG[15].reg |= PORT_PINCFG_PMUXEN;

To understand why you failed to get GCLK0 output to PA15 you need to study "I/O Multiplexing and Considerations". It depends on having a GCLK_IO for the pin you want to use (function H in the table). So it is not by accident I use GCLK1 for the 3 MHz (GCLK_IO[1] is a function available for PA15).

/Lars