SAMD21 How to unstop a TC

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In order to change the TC->EVCTRL.EVACT value one has to disable the TC. As a result the STATUS.STOP bit is set. This is supposed to be cleared when one writes a RETRIGGER command to CTRLBSET.CMD (see section 30.6.2.5.2 of the datasheet)

There are two problems:

1. TC->COUNT is cleared on disabling the TC

2. The STATUS.STOP bit is not cleared on issuing the CTRLBSET.RETRIGGER command, so the counter doesn't continue counting

 

The TC was running until the program hit the following code.

TC5->COUNT16.CTRLA.reg &= ~TCC_CTRLA_ENABLE;  /* Disable TC */
while (TC5->COUNT16.STATUS.bit.SYNCBUSY)	/* Must sync */
	;
/* COUNT was cleared by the disable */
TC5->COUNT16.EVCTRL.bit.EVACT = TC_EVCTRL_EVACT_RETRIGGER_Val;
while (TC5->COUNT16.STATUS.bit.SYNCBUSY)
	;
TC5->COUNT16.CTRLA.reg |= TCC_CTRLA_ENABLE;  /* Enable TC */
while (TC5->COUNT16.STATUS.bit.SYNCBUSY)	/* Must sync */
	;
/* STOP bit still set here */

There are no relevant errata about TC

Any ideas?

Best wishes, Jerry

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Note:  When a re-trigger event action is configured in the Event Action bits in the Event Control register (EVCTRL.EVACT=0x1, RETRIGGER), enabling the counter will not start the counter. The counter will start on the next incoming event and restart on corresponding following event.

So do you have a configured event that will start it and it still does not start or?

/Lars

 

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Lajon wrote:
So do you have a configured event that will start it and it still does not start or?

Hello Lars,

    Thanks for the quick reply, I'm slow in answering it because I was away yesterday.

I took another look at the datasheet and read it with more attention, then tested the program again - the retriggered timer didn't restart at all, even after lots of events.

As it turned out, the program can't tolerate even one delay between events. The retriggered timer provides an internal clock, which is synchronised with the PPS signal from a GPS

I've changed the program design so that synchronisation is maintained without the retrigger action

Best wishes, Jerry

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Hi,
Please help me to start the TC3:
TC is initialized as follows(IDE: MPLAB X, Compiler XC32)

I have used atmel START to generate driver layer code:
 

int8_t TIMER_0_init()
{

    hri_tc_wait_for_sync(TC3);
    if (hri_tc_get_CTRLA_reg(TC3, TC_CTRLA_ENABLE)) {
        hri_tc_clear_CTRLA_ENABLE_bit(TC3);
        hri_tc_wait_for_sync(TC3);
    }
    hri_tc_write_CTRLA_reg(TC3, TC_CTRLA_SWRST);
    hri_tc_wait_for_sync(TC3);

    hri_tc_write_CTRLA_reg(TC3,
                           1 << TC_CTRLA_PRESCSYNC_Pos       /* Prescaler and Counter Synchronization: 1 */
                               | 0 << TC_CTRLA_RUNSTDBY_Pos  /* Run in Standby: disabled */
                               | 3 << TC_CTRLA_PRESCALER_Pos /* Setting: 3 */
                               | 0 << TC_CTRLA_WAVEGEN_Pos   /* Waveform Generation Operation: 0 */
                               | 0x0 << TC_CTRLA_MODE_Pos);  /* Operating Mode: 0x0 */

    // hri_tc_write_CTRLB_reg(TC3,0 << TC_CTRLBSET_CMD_Pos /* Command: 0 */
    //         | 0 << TC_CTRLBSET_ONESHOT_Pos /* One-Shot: disabled */
    //         | 0 << TC_CTRLBSET_DIR_Pos); /* Counter Direction: disabled */

    // hri_tc_write_CTRLC_reg(TC3,0 << TC_CTRLC_CPTEN1_Pos /* Capture Channel 1 Enable: disabled */
    //         | 0 << TC_CTRLC_CPTEN0_Pos); /* Capture Channel 0 Enable: disabled */

    hri_tc_write_READREQ_reg(TC3,
                             1 << TC_READREQ_RREQ_Pos        /*  Read Request: enabled */
                                 | 0 << TC_READREQ_RCONT_Pos /*  Read Continuously: disabled */
                                 | 0x0);                     /* Address: 0x0 */

    hri_tc_write_DBGCTRL_reg(TC3, 1); /* Run in debug: 1 */

    // hri_tccount16_write_CC_reg(TC3, 0 ,0x0); /* Compare/Capture Value: 0x0 */

    // hri_tccount16_write_CC_reg(TC3, 1 ,0x0); /* Compare/Capture Value: 0x0 */

    // hri_tccount16_write_COUNT_reg(TC3,0x0); /* Counter Value: 0x0 */

    hri_tc_write_EVCTRL_reg(
        TC3,
        0 << TC_EVCTRL_MCEO0_Pos       /* Match or Capture Channel 0 Event Output Enable: disabled */
            | 0 << TC_EVCTRL_MCEO1_Pos /* Match or Capture Channel 1 Event Output Enable: disabled */
            | 0 << TC_EVCTRL_OVFEO_Pos /* Overflow/Underflow Event Output Enable: disabled */
            | 1 << TC_EVCTRL_TCEI_Pos  /* TC Event Input: enabled */
            | 0 << TC_EVCTRL_TCINV_Pos /* TC Inverted Event Input: disabled */
            | 3);                      /* Event Action: 3 */

    // hri_tc_write_INTEN_reg(TC3,0 << TC_INTENSET_MC0_Pos /* Match or Capture Channel 0 Interrupt Enable: disabled */
    //         | 0 << TC_INTENSET_MC1_Pos /* Match or Capture Channel 1 Interrupt Enable: disabled */
    //         | 0 << TC_INTENSET_SYNCRDY_Pos /* Synchronization Ready Interrupt Enable: disabled */
    //         | 0 << TC_INTENSET_ERR_Pos /* Error Interrupt Enable: disabled */
    //         | 0 << TC_INTENSET_OVF_Pos); /* Overflow Interrupt enable: disabled */

    hri_tc_write_CTRLA_ENABLE_bit(TC3, 1 << TC_CTRLA_ENABLE_Pos); /* Enable: enabled */

    return 0;
}