SAMA5D2 - SPI delay between bytes

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I've found that SPI transfers (with and without DMA) at 20MHz have a delay between the bytes - about 178ns with DMA, longer without using DMA. This occurs when running my own code and running the softpack V2.15 SPI slave example (with frequency changed to 20MHz) on the SAMA5D2-XULT development board.

It's very important for this application that I can perform SPI transfers as fast as possible.

 

Processor: SAMA5D27-CU
Processor clock: 498 MHz
Master clock: 166 MHz
MMU is enabled
I-Cache is enabled
D-Cache is enabled
L2-Cache is disabled

 

Has anyone else noticed this issue? Any help or experience with this issue would be appreciated.

Last Edited: Mon. Sep 23, 2019 - 05:15 PM
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In searching for answers to a similar problem on a SAM4S, I ran across your post.  See if the problem I'm having could be the same issue for you:

 

https://community.atmel.com/forum/sam4s-usart-spi-master-pdc-dma-delay-between-tx-bytes

 

Duncan