AVR Freaks

Bare code here, but note most likely you will want to control the chip select manually (and not using the SERCOM SPI like in the example).  So MSSEN=0 and not setting up pin muxing for that pin (PA18 in the example).

#include "sam.h"

void spiInit(void)
{
    PM->APBCMASK.bit.SERCOM1_ = 1;
    GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_ID_SERCOM1_CORE;
    while(GCLK->STATUS.bit.SYNCBUSY);
    const SERCOM_SPI_CTRLA_Type ctrla = {
      .bit.DORD = 0, // MSB first
      .bit.CPHA = 0, // Mode 0
      .bit.CPOL = 0,
      .bit.FORM = 0, // SPI frame
      .bit.DIPO = 3, // MISO on PAD[3]
      .bit.DOPO = 0, // MOSI on PAD[0], SCK on PAD[1], SS_ on PAD[2]
      .bit.MODE = 3  // Master
    };
    SERCOM1->SPI.CTRLA.reg = ctrla.reg;
    const SERCOM_SPI_CTRLB_Type ctrlb = {
      .bit.RXEN = 1,   // RX enabled
      .bit.MSSEN = 1,  // HW SS
      .bit.CHSIZE = 0 // 8-bit
    };
    SERCOM1->SPI.CTRLB.reg = ctrlb.reg;	

    SERCOM1->SPI.BAUD.reg = 0; // Rate is clock / 2 

    // Mux for SERCOM1 PA16,PA17,PA18,PA19
    const PORT_WRCONFIG_Type wrconfig = {
      .bit.WRPINCFG = 1,
      .bit.WRPMUX = 1,
      .bit.PMUX = MUX_PA16C_SERCOM1_PAD0,
      .bit.PMUXEN = 1,
      .bit.HWSEL = 1,
      .bit.PINMASK = (uint16_t)((PORT_PA16 | PORT_PA17 | PORT_PA18 | PORT_PA19) >> 16)
    };
    PORT->Group[0].WRCONFIG.reg = wrconfig.reg;

    SERCOM1->SPI.CTRLA.bit.ENABLE = 1;
    while(SERCOM1->SPI.SYNCBUSY.bit.ENABLE);
}

uint8_t spiSend(uint8_t data)
{
    while(SERCOM1->SPI.INTFLAG.bit.DRE == 0);
    SERCOM1->SPI.DATA.reg = data;
    while(SERCOM1->SPI.INTFLAG.bit.RXC == 0);
    return SERCOM1->SPI.DATA.reg;
}

int main(void)
{
    SystemInit();
    spiInit();

    volatile uint8_t rData;
    volatile uint8_t sData = 0;
    while (1) {
      rData = spiSend(sData++);
    }
}

/Lars

Hello, thanks Lars for posting the example code. The example code works for me, but when I try to change it to work for SERCOM0 with MOSI on pad0 (PA08), SCLK on pad1 (PA09), CS on pad2 (PA10), and MISO on pad3 (PA11). When I run in debug mode all the code executes and seems to run, but none of the pins are outputting anything which makes me think I am not setting up the pins or pin mux correctly. Below is my code, would greatly appreciate any help.

void spiInitSERCOM0(void)
{
	PM->APBCMASK.bit.SERCOM0_ = 1;
	GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_ID_SERCOM0_CORE;
	while(GCLK->STATUS.bit.SYNCBUSY);
	const SERCOM_SPI_CTRLA_Type ctrla = {
		.bit.DORD = 0, // MSB first
		.bit.CPHA = 0, // Mode 0
		.bit.CPOL = 0,
		.bit.FORM = 0, // SPI frame
		.bit.DIPO = 3, // MISO on PAD[3]
		.bit.DOPO = 0, // MOSI on PAD[0], SCK on PAD[1], SS_ on PAD[2]
		.bit.MODE = 3  // Master
	};
	SERCOM0->SPI.CTRLA.reg = ctrla.reg;
	const SERCOM_SPI_CTRLB_Type ctrlb = {
		.bit.RXEN = 1,   // RX enabled
		.bit.MSSEN = 1,  // HW SS
		.bit.CHSIZE = 0 // 8-bit
	};
	SERCOM0->SPI.CTRLB.reg = ctrlb.reg;

	SERCOM0->SPI.BAUD.reg = 0; // Rate is clock / 2

	// Mux for SERCOM0 PA08,PA09,PA10,PA11
	const PORT_WRCONFIG_Type wrconfig = {
		.bit.WRPINCFG = 1,
		.bit.WRPMUX = 1,
		.bit.PMUX = MUX_PA08C_SERCOM0_PAD0,
		.bit.PMUXEN = 1,
		.bit.HWSEL = 0,
		.bit.PINMASK = (uint16_t)((PORT_PA08 | PORT_PA09 | PORT_PA10 | PORT_PA11) >> 16)
	};
	PORT->Group[0].WRCONFIG.reg = wrconfig.reg;

	SERCOM0->SPI.CTRLA.bit.ENABLE = 1;
	while(SERCOM0->SPI.SYNCBUSY.bit.ENABLE);
}

uint8_t spiSend0(uint8_t data)
{
	while(SERCOM0->SPI.INTFLAG.bit.DRE == 0);
	SERCOM0->SPI.DATA.reg = data;
	while(SERCOM0->SPI.INTFLAG.bit.RXC == 0);
	return SERCOM0->SPI.DATA.reg;
}

int main(void)
{
	SystemInit();
	spiInitSERCOM0();
	delay_init();

	volatile uint8_t rData;
	volatile uint8_t sData = 0;
	while (1) {
		delay_ms(1);
		rData = spiSend0(MAX31856_CONFIG_REG);
		rData |= MAX31856_CONFIG_3WIRE;
		//spiSend1(rData);
	}
}

That makes sense and it worked. Thank you Lars

You don't say what is not working but I notice a problem with the port setting: WRCONFIG can't configure your pins with one register write, you need one write for PA00,PA01 (HWSEL = 0) and one for PA30,PA31 (HWSEL = 1 and the bitmasks shifted down 16).
/Lars