SAM D21 Clock System: OSC8M->CLKGEN->SYSCTRL->CPU

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I'm trying to get a good grip on the SAM D clock systems. Had to start somewhere so I picked the D21 (over the D20, after a remark by Alex Taradov on the EEVblog forums).

 

There are a lot of questions I might come up with eventually, but here is a first "set":

 

While not being explicitly illustrated in any figure the data sheet says, if I read it correctly, that the OSC8M clock source has a "built in" prescaler. I infer this from a formulation that I know Iäve read (but can not locate again, sigh, that is a complex data sheet!).

The OSC8M can be fed into a Generic Clock Generator, and this includes GCLKGEN0.

 

GCLKGEN0, in turn, is the source for the GCLK_MAIN clock signal that goes into the SYSCTRL module. There it passes a prescaler before being routed to the CPU as CLK_SPU.

 

So, aim I correct if I say that the OSC8M oscillator can pass three prescalers on it's way to be (one alternative for) the CPU clock?!

 

The data sheet says that the default startup CPU clock is "OSC8M divided by eight". Is the divide by eight done by the prescaler in the SYSCTRL module?

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Not that I have a very clear picture of the whole clock system, but I will take a shot anyway:
- GCLKGEN0 is GCLK_MAIN
- I count only two OSC8M prescalers: SYSCTRL->OSC8M.bit.PRESC and GCLK->GENDIV
- The divide by 8 is in SYSCTRL->OSC8M.bit.PRESC (see the reset value, it is 11)


Edit: "power value" -> "reset value"

Last Edited: Sat. Dec 9, 2017 - 11:00 PM
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OK, I see that there is also PM->CPUSEL. I've never used that one. Then it is indeed three prescalers.

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ezharkov wrote:
GCLKGEN0 is GCLK_MAIN

Yes, GCLK_MAIN comes from GCLKGEN0 but the data sheet shows that there is a clock mux on the SYSCTRL clock input. One is GCLK_MAIN, the other is direct from OSC8M. I assume that the latter is selected at power up.

 

There is a prescaler in SYSCTRL that has 8 different prescaling options. See figure 16-2. Thi figure shows only one input to the mux before the prescaler. But somewhere (again, I lost the reference) I'm sure the sheet says (or implies or shows) that OSC8M can be routed directly to the SYSCTRL input. (And if there aren't several inputs, then there would be no need for a mux on the input, right?)

 

Anyway, as you note the control register for the OSC8M clock source has a field for controlling a prescaler that

i) thus is specific to the OSC8M, and

ii) has four prescaling options

 

Figure 16-2 shows a prescaler with eight options (so this is not the OSC8M prescaler). Which register controls that prescaler? I haven't been able to locate it in the data sheet. (I'm tired so this might be temporary blindness...) To be more precise, the CPU and each APB bus controller has a mux selecting a one of the clock signals out of that prescaler, so which register is used for muxing those prescsled clocks into, say, the CLK_CPU signal?

 

Aside: Boy is this a hard data sheet to read! Anyone ever complaining over the AVR(8) data sheets being hard to read should spend a few hours with a SAM D sheet and they will never again whine over an AVR(8) sheet!

As of January 15, 2018, Site fix-up work has begun! Now do your part and report any bugs or deficiencies here

No guarantees, but if we don't report problems they won't get much of  a chance to be fixed! Details/discussions at link given just above.

 

"Some questions have no answers."[C Baird] "There comes a point where the spoon-feeding has to stop and the independent thinking has to start." [C Lawson] "There are always ways to disagree, without being disagreeable."[E Weddington] "Words represent concepts. Use the wrong words, communicate the wrong concept." [J Morin] "Persistence only goes so far if you set yourself up for failure." [Kartman]

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I think the prescaler in Figure 16-2 is PM->CPUSEL.bit.CPUDIV.

AVR vs this ... I'm OK with the clock system. But synchronization! That looks like a total mess to me. You need to jump through hoops just to read the TCC counter.

Last Edited: Sat. Dec 9, 2017 - 11:27 PM
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ezharkov wrote:
But synchronization! That looks like a total mess to me. You need to jump through hoops just to read the TCC counter.

I was about to point you to a discussion in Alex Taradovs https://github.com/ataradov/mcu-... re synchronization. Then I saw who Alex was discussing with... (-:

 

In line with the discussion there, if you are sure you don't access the TCC counter "too often" then you'd get by without the hoops? Then the question arises: What is "not too often" in terms of time? I guess the answer is "the synchronization in progress bit tells you". But there must be some longish time that will be more than enough for not risking a bus error..

As of January 15, 2018, Site fix-up work has begun! Now do your part and report any bugs or deficiencies here

No guarantees, but if we don't report problems they won't get much of  a chance to be fixed! Details/discussions at link given just above.

 

"Some questions have no answers."[C Baird] "There comes a point where the spoon-feeding has to stop and the independent thinking has to start." [C Lawson] "There are always ways to disagree, without being disagreeable."[E Weddington] "Words represent concepts. Use the wrong words, communicate the wrong concept." [J Morin] "Persistence only goes so far if you set yourself up for failure." [Kartman]

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JohanEkdahl wrote:

In line with the discussion there, if you are sure you don't access the TCC counter "too often" then you'd get by without the hoops? Then the question arises: What is "not too often" in terms of time? I guess the answer is "the synchronization in progress bit tells you". But there must be some longish time that will be more than enough for not risking a bus error..

True in general but the TCC counter needs a special command, you really need to jump through hoops.

 

http://www.eevblog.com/forum/microcontrollers/atmel-sam-d-tc-and-tcc-(no-asf)/msg1065946/#msg1065946

/Lars

Last Edited: Sun. Dec 10, 2017 - 09:36 AM
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Aha! Two of the heavy-wheights in the same thread!

 

Yes, I was thinking (assuming, which I often tell others is bad...) the general case and was not aware the TCC is different.

 

Need to dig into the sheet to see if this is true for the simpler TC also, unless you know off-hand..

As of January 15, 2018, Site fix-up work has begun! Now do your part and report any bugs or deficiencies here

No guarantees, but if we don't report problems they won't get much of  a chance to be fixed! Details/discussions at link given just above.

 

"Some questions have no answers."[C Baird] "There comes a point where the spoon-feeding has to stop and the independent thinking has to start." [C Lawson] "There are always ways to disagree, without being disagreeable."[E Weddington] "Words represent concepts. Use the wrong words, communicate the wrong concept." [J Morin] "Persistence only goes so far if you set yourself up for failure." [Kartman]

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TC is simpler, no special sync command (also means the updating counter is visible in the debugger, for TCC this is only the case if the sync command is used).

/Lars

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Thank you, Lars! Saved me some time.  (-:

As of January 15, 2018, Site fix-up work has begun! Now do your part and report any bugs or deficiencies here

No guarantees, but if we don't report problems they won't get much of  a chance to be fixed! Details/discussions at link given just above.

 

"Some questions have no answers."[C Baird] "There comes a point where the spoon-feeding has to stop and the independent thinking has to start." [C Lawson] "There are always ways to disagree, without being disagreeable."[E Weddington] "Words represent concepts. Use the wrong words, communicate the wrong concept." [J Morin] "Persistence only goes so far if you set yourself up for failure." [Kartman]

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What about this:

OSC8M -> GCLK2 ->DFLL48M -> GCLK1 -> GCLK0 -> GCLK_MAIN

cheeky