I'm trying to get a good grip on the SAM D clock systems. Had to start somewhere so I picked the D21 (over the D20, after a remark by Alex Taradov on the EEVblog forums).
There are a lot of questions I might come up with eventually, but here is a first "set":
While not being explicitly illustrated in any figure the data sheet says, if I read it correctly, that the OSC8M clock source has a "built in" prescaler. I infer this from a formulation that I know Iäve read (but can not locate again, sigh, that is a complex data sheet!).
The OSC8M can be fed into a Generic Clock Generator, and this includes GCLKGEN0.
GCLKGEN0, in turn, is the source for the GCLK_MAIN clock signal that goes into the SYSCTRL module. There it passes a prescaler before being routed to the CPU as CLK_SPU.
So, aim I correct if I say that the OSC8M oscillator can pass three prescalers on it's way to be (one alternative for) the CPU clock?!
The data sheet says that the default startup CPU clock is "OSC8M divided by eight". Is the divide by eight done by the prescaler in the SYSCTRL module?