M7 (S70/E70/V70) power-on slope for Vdd

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The S70/E70/V70 has a steep power-on (turn on) requirement.  Vdd for the IC must reach 3.3V no sooner than 0.11ms and no later than 1.7ms when power is applied to the IC.  That is, the window for Vdd to reach 3.3V is 0.11ms to 1.7ms.  No sooner and no later.  This seems like a steep requirement.  Is this correct?  For those using a S70/E70/V70, how do you include this in your design? 

 

3.3V / (1.9V/ms) = 1.7ms

3.3V/ (30V/ms) = 0.11ms

 

The rise time of Vdd for M7 must be in this window.

Last Edited: Thu. Apr 14, 2016 - 10:15 PM