The Confusion of Periodic Interval Timer (PIT)

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I use SAMA5D2 as our system controller,  the Periodic Interval Timer (PIT) application make me confuse.


When SAMA5D2  enter  ULP0 state, the frequency of the clock is reduced in order to reduce power consumption. This results in that it will change in the PIT interrupt cycle (PIT uses MCK as the input clock).

If get the same interrupt cycle of PIT, only way is adjust the PIT cycle after enter  ULP0 state. But PIT counter can not stop when PIT is disable. So when enable the PIT again, the first  interrupt cycle of PIT is not we set.

What is importance: PIT counter can be reset only when PIT counter overflow and PIT counter can not be reset by manual. That may be the IC design Bug.

As for Linux, When SAMA5D2  enter  ULP0 state, how the Linux system deal with this issue to get the accurate time slice?

Any infor could help. Thanks.

Last Edited: Sat. Mar 11, 2017 - 10:23 AM