This question is distressingly familiar, but even after re-reading https://community.atmel.com/foru... carefully, I'm still stuck...
Short form:
I'm trying to configure SAMD21 Xplained Pro to run at 48Mhz via:
XOSC32K (32KHz) => GCLK3 (32KHz) => DFLL48M (47.972MHz) => GCLK0 (47.972) => CPU
It is hanging inside hri_gclk_wait_for_sync() while configuring GCLK3.
Details:
I'm using Atmel START with the following settings on the CLOCKs screen:
(In the following list, mentioning the setting means "enabled" and not mentioning means "disabled", except as noted otherwise):
XOSC32K:
External 32K Oscillator Enable
Run In Standby
Enable 32KHz output
Enable XTAL (tried both enabled and disabled -- no change)
Automatic Amplitude Control Enable: DISABLED (as per errata)
Start up time for the 32K Oscillator: 62592 us
GCLK3:
Run in Standby
Output Enable
Generic Clock Generator Enable
Generic clock generator 3 source: 32Khz External Crystal Oscillator (XOSC32K)
Generic clock generator 3 division: 1
DFLL48M:
Reference Clock Source: Generic clock generator 3
DFLL Enable
On Demand (also tried disabling, no change)
Operating Mode Selection: Closed Loop Mode
DFLL Multiple factor: 1464 (thank you, Lars...)
GCLK0:
Output Enable
Generic Clock Generator Enable
Generic clock generator 0 source: Digital Frequency Locked Loop (DFLL48M)
Generic clock generator 0 division: 1
Other stuff:
NVM Wait States: 1 (also tried 3 wait states, no change)
The Ask:
Any idea what I'm missing? Would any of the config files be useful?