Cannot able to generate clock using FPLL0 in ATSAMD51 controller

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Hello,

I have Metro M4 Grand Central board that contains ATSAMD51P20A controller. I'm using Atmel Studio 7.0 as IDP and Atmel Start as a configurator. I'm new to Atmel product so do not know much about the use of IDP and configurator but figured out by some study.

The board has a 32Khz external crystal and by using Atmel Start I create a project that generates 48MHz CPU clock through DFLL open-loop configuration. I build and RUN the code inboard and blink the LED to check the working. This configuration works fine.

As per the datasheet if you want to increase the clock speed you have to use DPLL as DFLL48M can go up to 48MHz if I'm not wrong. For that, I reconfigure the same code using Atmel start and use DPLL0 to generate 119.997MHz as you can find in the attached snaps. Here when I debug the code it struct in hpl_oscctrl.c file inline
while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw, 0) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw, 0)))

So far I understand, Lock bit cause some issue here or the clock is not yet ready to functioning. However, If I program the code to the device it will blink LED successfully. I search many examples in Atmel Start and use the same configuration but it has the same result.

So, now I'd run out of ideas. Please suggest some solution to this issue.
 

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Last Edited: Mon. Aug 10, 2020 - 12:00 PM