BPSK demodulation using an ATMEL microcontroller

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Hello,

I wish to retrieve data from a BPSK signal, using a digital approach under ATMEL.
This signal is the feedback from a Märklin decoder used in model railway. Carrier frequency around 52kHz. Bit duration 912uS.

I whould like to know if any one as implemented BPSK demod on an ATMEL or know how this could be done.

A way is using a Costas loop, an other one is with "the optimal bpsk demodulator with a 1 bit a d front end".

Info appreciated
Pierre Moulin

Last Edited: Fri. Oct 16, 2015 - 02:04 PM
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I've implemented BPSK modem for different application with different parameters. There are simpler ways than a Costas loop (which is hard to tune), but you still need to know a great deal of math.

Do you have more information about the signal? Do you have a way to get into the MCU already?

NOTE: I no longer actively read this forum. Please ask your question on www.eevblog.com/forum if you want my answer.

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alexru wrote:
I've implemented BPSK modem for different application with different parameters. There are simpler ways than a Costas loop (which is hard to tune), but you still need to know a great deal of math.

Do you have more information about the signal? Do you have a way to get into the MCU already?

> Do you have more information about the signal?
yes, I even have a .wav recorded. Attachment is an extract of 640mS.
I have tested the demodulation under skilab, a simple multiply by LocalOscillator at a known frequency. It works as a proof of concept.
Each sequence of data is transmitted during 42mS. First half is for sync purposes. Second half is with the BPSK. 23 bit are transmitted.
The analog demodulation is done with a RDS circuit, see schematic attached. It is true that the analog IC uses a costas loop, but it is not necessary to mimic the IC!
The carrier frequency correspond to a frequency derived from a quartz with one „straight “frequency value: 4 MHz The carrier frequency amounts to 52.63 kHz (results from 4 MHz divided by 76, instead of 4.332 MHz divided by 76 = 57 kHz in the case of RDS®) period 19 µs.

> Do you have a way to get into the MCU already
I suppose that the MCU is the ATMEL on which I would like to implement the algorithm, the aim being to replace the analog IC by a full digital solution (except for the acquisitio of signal of course)
The existing hardware uses a ATxmega128A1.
I don't have the hardware at hand just now. Will it make sense to test the algoritm under scilab (I don't have matlab) before moving to real implementation. A way to learn step by step. :)

> you still need to know a great deal of math
I learnt electronic at high school in France some times ago 1968, but I learn every day thanks to internet and google :idea: .

Thanks for help
Pierre

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So the idea of the receiver is simple:
1. Multiply your input signal by sin(LO) cos(LO), where lo is a local oscillator. Sort of what you did, but you need to have both I and Q components.
2. Filter I and Q to get rid of double-frequency components.
3. Calculate output components like (I might have made a mistake here, you'll have to double check):

Iout = I*Qa - Q*Ia
Qout = Q*Qa + I*Ia;

where Ia = cos(alpha) and Qa = sin(alpha), 'alpha' is a correction angle. You need tune alpha so that one of the components Iout or Qout is close to 0, this way another component will contain demodulated data.

LE: By 'tune' here I mean not by hand, but using locked loop. Like Costas, only much simpler.

There are ways to improve this algorithm, but since you are not dealing with low SNRs it will probably works fine.

I'm attaching a BPSK modem that I've made a few years back, it is working and was implemented in FPGA, but it is not directly applicable for this case. It is a Matlab file, forum does not allow .m extension.

Attachment(s): 

NOTE: I no longer actively read this forum. Please ask your question on www.eevblog.com/forum if you want my answer.

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Thanks for answer. I will have a look at your modem after translating from Matlab to scilab.

Quote:
By 'tune' here I mean not by hand, but using locked loop. Like Costas, only much simpler.

In BPSK one does not have the carrier, so the costas. Do you mean a PLL that you lock on "one of the components Iout or Qout is close to 0". May be I will have an answer in your modem

I am doing the algorithm for BPSK only part time, since at summer time we have people visiting us. I will keep you informed.

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peter_moulin wrote:
Thanks for answer. I will have a look at your modem after translating from Matlab to scilab.
It probably will be an overkill to translate everything, especially due to heavy use of functions like 'firls', which are not available in scilab.

peter_moulin wrote:
In BPSK one does not have the carrier, so the costas.
What do you mean? Phase of what changes then? Carrier frequency is a frequency of a local oscillator. But simple multiplication by LO (how you did) won't be enough, because of frequency shifts (Doppler effect and difference in frequencies on the transmitter and receiver) result won't be stable.

peter_moulin wrote:
Do you mean a PLL that you lock on "one of the components Iout or Qout is close to 0".
It is not exactly a PLL, just a loop that is tries to have one of the quadratures close to 0, which guarantees that the other one is at its maximum value.

Can you send an original signal file?

NOTE: I no longer actively read this forum. Please ask your question on www.eevblog.com/forum if you want my answer.

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Quote:
It probably will be an overkill to translate everything

I had just started to try to use mfile2sci.
Quote:
What do you mean? ...In BPSK one does not have the carrier

BPSK is equivalent to a Coherent amplitude modulation, carrier does not exist in the spectrum to my understanding.

Find attached an example done after frequency translation ( an analog multiply) so I could sample with my audio input. It is a .wav file sampled at 22050, extracted from a sequence when the train decoder was sending data. The 58.9 in the name means that I used a 58.9khz LO to down convert the incoming signal. Filtering is done by the PC sampling input filter ( half Nyquist). Since the LO is not exactly 58.9 ( an old analog generator) I found the resulting translation at 6086Hz

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Bonjour,

Some suggested the following:

"when riding on the train home, I thought of a different approach:

Sample the signal with 250kHz, and use a 19 tap long sinosoidal waveform comprimising sin and cos of 52kHz (4 cycles) and make a discrete convolution. (makes 38 MACs per sample point) This would shift the waveform to DC. Now make a FIR lowpass in both I and Q to get rid of unwanted spurs and sample data at twice the bitrate. Depending on frequency error the sample point needs shifting - this could be done with an eye catcher. Last step is to do the exor to recover biphase coding."

Does this make sense to you or does this ring a bell?
52kHz is the carrier frequency.
I can't see how the convolution would shift the waveform to DC.

The above just for a possible advice, don't spend too much time on it.

Regards

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alexru wrote:
So the idea of the receiver is simple:
.....

I'm attaching a BPSK modem that I've made a few years back, it is working and was implemented in FPGA, but it is not directly applicable for this case. It is a Matlab file, forum does not allow .m extension.

Latest infos:

I found two articles
one from ZIPcores BPSK_DEMOD http://www.zipcores.com/skin1/zipdocs/datasheets/bpsk_demod.pdf
and the other one from http://homes.jcu.edu.au/~eecjk/research/ICICS99-275BPSK.pdf

I have simulated the first one under scilab and it works. I mean I retrieve the data from the sample signal I send you.
I have simulated the architecture, not yet a possible implementation on ATMEL.
I might try the second one too.

Regards
Pierre

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Both methods rely on having directly sampled signal. The way you do down-conversion (simple multiplication and filtering) may result in 0 output depending on a phase shift between the local oscillator and received signal. In this case there will be nothing to recover for BPSK demodulator. That is why my model is so complicated - it uses both I and Q quadratures and combines signal from both.

The first method will only work with relatively large SNR, which is not a problem in your case.

The second one relies on accurate and tunable ADC sampling rate (integer number of samples must fit into into the delay line). Thai is why they also have a PLL tune output, which must be fed back to the ADC.

So the first method is fine for this case, as long as you can make sure that signal is sampled directly and is not down-converted or down-converted in quadratures.

For direct conversion you will probably need at least 200 ksps ADC.

NOTE: I no longer actively read this forum. Please ask your question on www.eevblog.com/forum if you want my answer.

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Hello,

Quote:
The way you do down-conversion (simple multiplication and filtering)
That was just for ADC hardware (PC) compatibilty.
Quote:
For direct conversion you will probably need at least 200 ksps ADC
The German guy, I am in contact with, suggest "Sample the signal with 250kHz" on an ATxmega128A1. Should be feasable if I understand its advice.
Quote:
Both methods rely on having directly sampled signal
Which means that if I can sample at 250kHz I don't need to introduce I & Q.

Thanks for your comments
Pierre