It stuck at this line:
while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw)))
The code was created from START. The clock tree:
The PLL reference is 1MHz (required 0.3 to 2MHz), which is created from internal 8MHz oscillator /8.
The DPLL feedback divider is 63, and it should output 64MHz (32MHz to 96MHz) clock , after /2, it becomes 32MHz as CPU clock.
I tried an external clean and stable clock source 8MHz (replacing the internal 8MHz oscillator), it had same symptom. Attached are the .atstart and .atzip files.