ATSAML11E16A DPLL does not lock

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It stuck at this line:

                while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw)))

 

The code was created from START. The clock tree:

The PLL reference is 1MHz  (required 0.3 to 2MHz), which is created from internal 8MHz oscillator /8.

The DPLL feedback divider is 63, and it should output 64MHz (32MHz to 96MHz) clock  , after /2, it becomes 32MHz as CPU clock.

I tried an external clean and stable clock source 8MHz (replacing the internal 8MHz oscillator), it had same symptom. Attached are the .atstart and .atzip files.

Any Idea?

Thanks

 

 

 

 

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lxiu

Last Edited: Mon. Dec 16, 2019 - 08:44 PM
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This processor has two performance level settings, only performance level 2 (PL2) can support 32MHz CPU clock. PL0 only support up to 16MHz clock (there is no PL1). This could be the 2nd reason that it does not work. The first reason, that the PLL does not lock, is still unknown

lxiu

Last Edited: Tue. Dec 17, 2019 - 02:34 PM
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You need 1 or 2 NVM wait states at 32 MHz (this information is in "Electrical Characteristics"). It's a setting in MCLK for Atmel Start.

/Lars

 

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Lajon

  Thanks for the information. I tried NVM 2 wait states, still could not lock. NVM configuration is inside of CPU.

  To create 32MHz internal CPU clock, a DFLL looks working. The DFLL input is 32.768k internal oscillator, feedback divider 977. The CPU has to be configured as PL2.

  So far I still could not make the PLL working.

 

 

 

lxiu