ATSAME51N19 SWO not working properly

1 post / 0 new
Author
Message
#1
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Hi all,

 

I'm trying to get a decent SWO output from the ATSAME51N19A mcu I'm working with.

So far it's not working like it should.

 

I'm working with Microchip Studio V7.0.2542, CMSIS V5.4.0 and DFP 1.1.129 and 1.1.139

My debugger is a J-LINK Plus with a 6-pin Tag Connect

I've attached my current code.

 

I'm not getting any SWO data in both Microchip Studio and Ozone.

It partially works with J-Link SWO Viewer V6.98, but not in the way I'm expecting.

 

If I boot the SAME, open SWO Viewer, select ATSAME51N19 (Automatically sees 120MHz clkspeed) and press OK I can see the stream of B's that are in the while(1).

But if I then reboot the MCU I don't get any data at all. I have to go to edit -> Configure -> ok, and after that I get my stream of B's again.

I never see the A.

 

I've also tried Ozone V3.22.

Select device and SVD file, select Jlink, open .ELF and set trace to SWO with auto frequency for MCU and SWO

I can see the sourcecode, I can program and debug everything, but I don't get any SWO output, ever.

 

What can I do to fix this?

 

#define CM4_TRACE_GCLK_ID 47

#define CPU_FREQUENCY 120000000UL
#define SWO_PRINT_PORT 0
#define SWO_FREQUENCY 6000000UL
#define SWOPRESCALE (((CPU_FREQUENCY)/(SWO_FREQUENCY)) - 1)
#define ITM_ID ((1UL << ITM_TCR_TraceBusID_Pos) & ITM_TCR_TraceBusID_Msk)

void Initialize_SWO(void)
{
    CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; // enable access to the trace component registers.

    TPI->SPPR = 0x2UL; // Selected Pin Protocol Register -> Serial Wire Viewer, UART NRZ 
    TPI->ACPR = SWOPRESCALE;
    ITM->LAR = 0xC5ACCE55UL; // unlock the ITM
    ITM->TCR = ITM_TCR_ITMENA_Msk | ITM_TCR_TSENA_Msk | (1UL << ITM_TCR_TraceBusID_Pos)	| ITM_TCR_DWTENA_Msk | ITM_TCR_SYNCENA_Msk | ITM_TCR_SWOENA_Msk; // Enable ITM
    ITM->TER = 0xFFFFFFFF; // ITM Trace Enable Register 
    ITM->TPR = 0;
};

int main(void)
{
    REG_NVMCTRL_CTRLA |= NVMCTRL_CTRLA_RWS(6); //Set flash waitstates to 6
    REG_NVMCTRL_CTRLA &= ~NVMCTRL_CTRLA_AUTOWS; //Disable auto waitstates
    
    PORT->Group[1].DIRSET.reg |= PORT_PB30; 
    PORT->Group[1].PINCFG[30].reg |= PORT_PINCFG_PMUXEN;
    PORT->Group[1].PMUX[30/2].reg |= PORT_PMUX_PMUXE(0x07); //Set PB30 to CORTEX_CM4/SWO mux H

    XOSC32K_Initialize(); //Init external 32khz crystal
    FDPLL0_Initialize_120MHz(); //Set FDPLL0 to 120MHz and MCLK to DIV 0x01
    GCLKn_Initialize(GCLK_ID_0, GCLK_SRC_FDPLL0, 1); //Connect GCLK0 and MCLK to FDPLL0 at 120MHz
    REG_GCLK_PCHCTRL47 =  GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(0x00); //Connect GCLK0 to CM4_TRACE_GCLK_ID 
    while(!(REG_GCLK_PCHCTRL47 & GCLK_PCHCTRL_CHEN)) {__ASM("nop");} //Wait for synchronization

    Initialize_Systick(Systick_OVERFLOW_1000Hz); //1ms systick interrupt for Delay() function
    Initialize_SWO();

    Delay(500); //500ms delay

    ITM_SendChar('A');

    while(1)
    {
        Delay(100);
        ITM_SendChar('B');
    }
}