I2S with 2 DMA channels

Go To Last Post
2 posts / 0 new
Author
Message
#1
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Hi,

I have a HW that uses I2S bus, in 32b, Stereo mode,

i.e. data on output pin I2S/SD[0] are organized:  32b_L, 32b_R, 32b_L, 32b_R,...

My application uses only the L channel, R is not audible, so the routine that fills audio data into buffer (pointed by DMA descriptor) organizes data this way:

32b_sample[i], 0, 32b_sample[i+1], 0, 32b_sample[i+2], 0, 32b_sample[i+3], 0,...  i.e. every second sample is 0 (all sample to R channel).

 

It is not optimal usage of the buffers, as 50% is wasted for useless zero-samples.

According to datasheet  29.9.7 Serializer n Control, there is bit SERCTRL[0].DMA,

if DMA=1, then even- and odd-numbered slots use separate DMA channels.

 

And this is what I don't understand.

I currently have solution with I2S->SERCTRL[0].DMA=0  (i.e. single DMA channel used for even- and odd-numbered slots) and it works ok.

As a trigger is selected  DMAC->CHCTRLB.reg = 0x00802B00;

// TRIGSRC[5:0]=0x2B .. I2S TX 0 Trigger

 

Questions:

Q1) is it correct to expect that setting I2S->SERCTRL[0].DMA=1 would cause, that for example DMA Channel 0 could be used for L samples only, and Channel 1 for R samples only ?

Q2) if yes, which trigger must be selected for DMA[0] and for DMA[1] ? Should both be 0x2B (I2S TX 0 Trigger) ?

I don't understand how is then determined, which of the 2 DMA channels us used for L and for R channel.

 

I tried to set I2S->SERCTRL[0].DMA=1, use DMA Channels [0] and [1], both configured with trigger=0x2B,

descriptors of both DMA Channels have DSTADDR=I2S->DATA[0].reg,

but it doesn't work.

 

Is there anybody with experience with I2S->SERCTRL[0].DMA=1 ?

 

This topic has a solution.
Last Edited: Tue. Jul 27, 2021 - 01:09 PM
This reply has been marked as the solution. 
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

ok, obviously documentation for D21 is incomplete,

I found answer in datasheet for ATSAME5x_D5x_family / 51.6.8.1 DMA Operation (page 1900),

 

    // Table 51-3. I2C DMA Request Generation
    //   SERCTRLm.DMA     Mode         Slot Parity     DMA Request Trigger
    //   -------------------------------------------------------------------
    //             0      Receiver     all             I2S_DMAC_ID_RX_m
    //                    Transmitter  all             I2S_DMAC_ID_TX_m
    //   -------------------------------------------------------------------
    //             1      Receiver     even            I2S_DMAC_ID_RX_m
    //                                 odd             I2S_DMAC_ID_TX_m
    //                    Transmitter  even            I2S_DMAC_ID_TX_m
    //                                 odd             I2S_DMAC_ID_RX_m
    //   -------------------------------------------------------------------
 

So the 2 DMA channels do work with triggers I2S_DMAC_ID_TX_0 and I2S_DMAC_ID_RX_0.