I'm using Atmel Start to configure a 120Mhz clock for the CPU using the digital phase locked loop DPLL0. My board features an Atmel ATSAMD51J19 with a 32Khz external crystal oscillator that I've specified in the clock configuration to be the source for DPLL0. The following figure describes my clock configuration:
This is my DFLL0 configuration:
(I selected Lock Bypass and Wake Up Fast features per the recommendation in the datasheet errata.) According to the data sheet, the following formula is used to calculate the Loop Divider Ratio (LDR):
So, if fCLK_DPLL0 = 120Mhz, fCKR = 32KHz, and LDRFRAC = 0, the value that I should enter for LDR to get a 120MHz output is
(125,829,120 / 32,768) - 1 = 3,839
However, Atmel Start indicates the resulting clock is 125.829MHz. What am I doing wrong?