SAMA5D2 System-In-Package LPDDR2 problems

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I'm struggling to get the LPDDR2 DRAM working in a SAMA5D27C-LD2G system-in-package (so I'm confident it's not a SAMA5-to-DDR wiring problem).  I've checked and re-checked my MPDDRC-configuration code (AT91Bootstrap with careful adjustments), but it just doesn't work - basically, storing 0xFFFFFFFF to any DRAM location reads back as 0xFFFFFFFF, but storing 0x00000000 generally reads back as 0x5781734C or slight variations with more '1' bits (0x5791734C, 0x5781734D etc.).  Similarly 0x0000FFFF reads back as 0x5781FFFF, 0xFFFF0000 as 0xFFFF734C - it looks as though '1 bits are stored correctly, but '0's may be read back as '1's.

 

Enabling or disabling the L2 cache makes no difference - is this a clue?

 

So far I've spent over a day modifying MPDDRC register settings, changing the order of writing registers, reading the datasheets of the SAMA5 and the LPDDR2 and Microchip application-notes, and I've not been able to alter the behaviour at all.  Has anyone else seen this kind of issue?  Any suggestions?

 

Thank you,

Mike Haben

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A possible further clue:  reading the MPDDRC registers on power-up, after enabling peripheral clocks but before writing any MPDDRC configuration, the "Device Auto-initialization Status" read-only bit (DAI_IN_PROGRESS) in MPDDRC_MR is set, and it remains set indefinitely.  The datasheet is unclear as to which device (MPDDRC or the SDRAM itself) this bit refers to, or what auto-initialization procedure it monitors.  Any ideas?

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The DAI_IN_PROGRESS bit refers to the SDRAM part. See pg 22 from this Micron data sheet. http://static6.arrow.com/aropdfc...

 

I recommend trying your code on a demo board,  such as the ATSAMA5D27-SOM1-EK1, which makes use of the SIP version of ATSAMA5D27. My suspicion is a problem with the voltage rails on your PCB, although I have not used the ATSAM5D27 SIP variant, so consider that a bit of a shot in the dark.

Josh @ CIHOLAS Inc - We fill the gaps from chips to apps

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Thanks Josh, I hadn't spotted that in the DRAM datasheet - so if that bit is staying set, the DRAM isn't happy, and it's no surprise that it doesn't hold data correctly.

 

In fact we did develop our code on the ATSAMA5D27-SOM1-EK demo board, we're now at that painful stage of transitioning to a board/device with low-power DRAM (and lower voltage rails, so maybe I'll try tweaking them a bit higher...).

 

 

Best regards,  Mike H.