I'm struggling to get the LPDDR2 DRAM working in a SAMA5D27C-LD2G system-in-package (so I'm confident it's not a SAMA5-to-DDR wiring problem). I've checked and re-checked my MPDDRC-configuration code (AT91Bootstrap with careful adjustments), but it just doesn't work - basically, storing 0xFFFFFFFF to any DRAM location reads back as 0xFFFFFFFF, but storing 0x00000000 generally reads back as 0x5781734C or slight variations with more '1' bits (0x5791734C, 0x5781734D etc.). Similarly 0x0000FFFF reads back as 0x5781FFFF, 0xFFFF0000 as 0xFFFF734C - it looks as though '1 bits are stored correctly, but '0's may be read back as '1's.
Enabling or disabling the L2 cache makes no difference - is this a clue?
So far I've spent over a day modifying MPDDRC register settings, changing the order of writing registers, reading the datasheets of the SAMA5 and the LPDDR2 and Microchip application-notes, and I've not been able to alter the behaviour at all. Has anyone else seen this kind of issue? Any suggestions?