SAME51 - Verifying Flash...Failed! (Custom Board)

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Hi all,

 

I just received in boards that I had designed which are using the SAME51J20A as the main controller for a CAN bus data logger.. I am having a LOT of trouble getting it to properly verify the program after flashing. First here's a few details before I write up the rest of this post.

 

IDE - Atmel Studio 7

Programmer - Atmel-ICE using SWD

MCU - ATSAME51J20A being supplied with 3.3V from a power supply

 

The error I get can be seen below.. However, the address, expected, and actual values are always different after flashing.

 

Verifying Flash...Failed! address=0x00a6 expected=0x00 actual=0x30

 

I have read a couple threads about people using the D21 Xplained boards and having similar issues, but theirs are always saying the actual=0xFF (They were erasing the chips, but zero programming was happening afterwards).. My issue is that 1 out of 20 times I can get it to flash, and verify properly (Which my applications then runs and is seen by turning on an LED at startup). I've also had times where it programs, but fails to verify, yet the program still seems to be acting fine, and then the third and most common problem is where I program, fail to verify, and the program doesn't appear to run at all.

 

I am able to connect to the device, read the device signature, and read/modify fuses. The problem seems to be.. not intermittent (the inverse of that? lol).. I can SOMETIMES get it to flash and verify fine.. So I am thinking it has something to do with either the board layout, or my bench setup.

 

Hopefully you guys can help me out!

This topic has a solution.

murph

Debugging - Being a detective in a crime movie where you are also the murderer.

Last Edited: Fri. Jul 6, 2018 - 02:48 AM
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The first things that come to mind are ripple on 3.3V and the layout around the 1.8V core power.  If you used the switching regulator inductor, remove it and see if that helps.

jeff

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Hey Jeff,

 

So I will admit that I did have some mistakes on this initial board spin that could be playing into my problem.. 

 

- All of the VCCIO lines, etc are tied directly to 3.3 with no decoupling (yikes.. I know, but I thought it would be ok for this first build just to test out peripherals)

 

- VCORE is floating.. I am using the chip in linear mode and the datasheet says to attach decoupling capacitors to the pin in this case.. This was purely me not noticing the recommendation until after the board was ordered.

 

- I have no external clock.. I made a really poor assumption that an internal oscillator would be present, however, after ordering boards I noticed that the only internal low power 32kHz oscillator.. (I'm not sure if this is a problem, and the code given when creating the project seems to be a little misleading as they referencing the default core clock being at 48MHz).. The only thing I could think of here is that the default is feading the 32kHz osc into the DFLL to provide 48MHz to the CPU..

 

murph

murph

Debugging - Being a detective in a crime movie where you are also the murderer.

This reply has been marked as the solution. 
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- All of the VCCIO lines, etc are tied directly to 3.3 with no decoupling (yikes.. I know, but I thought it would be ok for this first build just to test out peripherals)

Survivable but you will have IO glitches.  Can solder a 100nF at each one...

- VCORE is floating.. I am using the chip in linear mode and the datasheet says to attach decoupling capacitors to the pin in this case.. This was purely me not noticing the recommendation until after the board was ordered. 

Add the caps.  This is likely your issue.  I have succeeded in soldering ultrafine wire to the QFN solder squish out. but you likely heard the expletives from where you sit...

Must have.

 

- I have no external clock.. I made a really poor assumption that an internal oscillator would be present, however, after ordering boards I noticed that the only internal low power 32kHz oscillator.. (I'm not sure if this is a problem, and the code given when creating the project seems to be a little misleading as they referencing the default core clock being at 48MHz).. The only thing I could think of here is that the default is feeding the 32kHz osc into the DFLL to provide 48MHz to the CPU..

You won't make CAN or USB work with that sloppy a clock, but feed it to the DPLL and make 120MHz.  I had to deadbug 32KHz external oscillators on my first board.

You can look up the good folks on Adafruit's #discord page to see if they finally gost stability out of the DFLL.  I was never happy with it.

I have made past posts here on that and the DPLL.  Someone corrected my code as well.  Definitely read the errata before fixing the clock so you fix it once.

jeff

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Thanks Jeff, this was just the feedback I was looking for..

 

I think I've quickly realized after getting these first boards that I need to go through and make some improvments.. I'll probably just go through and order a second rev since I have several things I need to address.

 

- Add decoupling on 3.3

- Add decoupling on VCORE

- Add external oscillator

 

I'll report back once I try a few more things and/or order corrected boards.

 

murph

Debugging - Being a detective in a crime movie where you are also the murderer.

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best to at least get through all the pin-based IO.  i had misread so many things that my first spin was a white wire mess.

jeff

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Yup, I believe everything else is good.. My only problem seems to be around decoupling and supplies. I went through and made the changes I said I would.. 

 

I put a 4.7uF cap on VDDCORE as the Datasheet suggests.. The E51J20A doesn't have a GNDANA.. Should I still place a 100nF between VDDCORE and GND.. or is the 4.7uF sufficient?

 

// I also added a 48MHz crystal, so that should take care of any clocking problems I have in the future

murph

Debugging - Being a detective in a crime movie where you are also the murderer.

Last Edited: Mon. Jun 11, 2018 - 01:30 AM
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I believe that the ground pin closest to VddANA is VssANA...  

 

If you are doing high end ADC then I would go 4.7uF + 100n + 100p

jeff

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Hmmm, when looking at the pinout for the E51J20A it specifically calls out VDDANA but not VSSANA..  I have no plan to use ADC modules, this device will be using nothing but peripheral buses and any sensors will be going through an external IC.. 

 

I still need to give my mosfet switching a look through before making a final pass of review and then ordering.. Separate problem but I seem to be getting partial voltages on my FET drains even though I should have zero. frown There's a reason I became a FW engineer and not a HW engineer lol.

murph

Debugging - Being a detective in a crime movie where you are also the murderer.

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I vaguely recall seeing another source that treated it as analog ground.  If unused, I would still tie VDDANA to VDD, etc.

 

what do you mean by partial voltages?  Do you mean they are somewhere away from 0V or 3.3V?  Maybe the Vgsth selection if off and they are in a linear region?

jeff

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Yea, I have two fets which are switching 3.3v, and a third switching 5v..

 

I'm getting .9V, 1.73V, and 5V on the three fets.. Using a PNP and highside switching, and the gates are tied to 3.3V.. So I SHOULD be measuring 0V at all of the drains.. I switched out to a different part number and the problem seems to persist...

 

This is getting pretty far off topic from the OP, but if you want to continue this convo, just message me.

 

murph

Debugging - Being a detective in a crime movie where you are also the murderer.

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Well Rev B of my boards finally came in and it appears that adding the necessary decoupling caps to VDDCORE solved my problem. Thanks for the help Jeff!

murph

Debugging - Being a detective in a crime movie where you are also the murderer.

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you are welcome.

jeff