SAMA5D27 Performance

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The SMAMA5D27 part is relatively well documented.

The data sheet is comprehensive and the evaluation kit makes it easy to get started with this device.

 

There are an amazing array of internal peripherals that have some documentation, but many details are not clear.

The crypto unit has a lot of information on performance, but the detail on how fast the crypto core is run is not obvious.

The performance of the various memories is also not so clear.  What is the overhead to get to Li, L2 or SRAM?

There are details, like the 256 bit register, is it truly in the register file or an alternate register file?

How fast can the crypto unit be clocked?  What is recommended speed?

 

Thanks for any suggestions of pointers.

Last Edited: Fri. Jun 8, 2018 - 12:20 AM
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The documentation on the core itself, including details like Cache Latency, would be provided by ARM:

http://infocenter.arm.com/help/i...

 

The clock rate details for all the peripherals are all given in chapter 10 of the datasheet.

 

Since you didn't call out a particular register, all I can say is that the "256-bit register" is probably implemented as 8 contiguous 32-bit registers.

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The Microchip datasheet has detailed timing for the crypto unit.

And the clock sources are also details.

 

The skinny is that SHA256 can run about 25 MB/s when the system is running an OS and peak out at about 60 MBps in a dedicated mode.

 

So far, no data on the performance of the memories or latencies to various buses.

 

Most of the interesting details are documented, but not made public.

 

Last Edited: Wed. Jul 18, 2018 - 01:32 AM