AVR Freaks

Yes, this http://asf.atmel.com/bugzilla/show_bug.cgi?id=3747 bug seems still to be valid...

I also tried USB Host Vendor example adapted for SAME70-XPLD board and it didn't work when CONF_BOARD_ENABLE_CACHE is defined.

In \src\ASF\sam\drivers\usbhs\usbhs_host.c, the example has CONF_BOARD_ENABLE_CACHE_AT_INIT (notice the different name) but defining it doesn't help: both RX and TX are affected.

For example at TX tried combinations of one or even both of the following (immediately after preparing the TX buffer, main_vendor_buf_out) but it didn't work:

_dcache_flush(main_vendor_buf_out, len /* tried even with full length 1024 */ );
_dcache_flush((void *)USBHS_RAM_ADDR, UHD_PIPE_MAX_TRANS); // 0xA0100000,0x8000=32KB

Same at RX no luck with any of these:

_dcache_invalidate(main_vendor_buf_in, in_payload_trans /* tried even with full length 1024, but the same */ );
_dcache_invalidate((void *)USBHS_RAM_ADDR, UHD_PIPE_MAX_TRANS); // 0xA0100000,0x8000=32KB

The first workaround was to flush whole d-cache: SCB_CleanDCache before USB TX, respectively flush+invalidate SCB_CleanInvalidateDCache after USB RX.

But this defeats the d-cache purpose (to flush 32KB entirely when I want to send just 49 bytes...).

The second workaround was to place the RX/TX buffers in a non-cacheable area:

//! Output buffer for vendor class test
#if defined MPU_HAS_NOCACHE_REGION
COMPILER_SECTION(".ram_usbnocache")
#else
COMPILER_ALIGNED(32)
#endif // MPU_HAS_NOCACHE_REGION
static uint16_t main_vendor_buf_out[MAIN_VENDOR_LOOPBACK_SIZE];

Where the area "ram_usbnocache" is defined in src\ASF\sam\utils\linker_scripts\same70\same70q21\gcc\flash.ld:

MEMORY
{
  rom (rx)  : ORIGIN = 0x00400000, LENGTH = 0x00200000
  ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x0005f000
  /* For ram_usbnocache, see MPU_HAS_NOCACHE_REGION and NOCACHE_SRAM_REGION_SIZE */
  ram_usbnocache (rwx) : ORIGIN = 0x2045f000, LENGTH = 0x00001000
}


/* Section Definitions */
SECTIONS
{
    .text :
    {
        ...
    } > rom

    /* heap section */
    .heap (NOLOAD):
    {
        ...
    } > ram

    /* For ram_usbnocache, see MPU_HAS_NOCACHE_REGION and NOCACHE_SRAM_REGION_SIZE */
    .ram_usbnocache (NOLOAD) :
    {
        . = ALIGN(32);
        *(.ram_usbnocache);
    } > ram_usbnocache 

    . = ALIGN(4);
    _end = . ;
    _ram_end_ = ORIGIN(ram) + LENGTH(ram) -1 ;
}

Ensure these in conf_board.h:

#define CONF_BOARD_ENABLE_CACHE
#define MPU_HAS_NOCACHE_REGION
#define CONF_BOARD_CONFIG_MPU_AT_INIT

Also in src\ASF\sam\drivers\mpu\mpu.h (needed in src\ASF\sam\boards\same70_xplained\init.c):

#define INNER_OUTER_NORMAL_NOCACHE_TYPE(x)  ((0x01 << MPU_RASR_TEX_Pos) | (DISABLE << MPU_RASR_C_Pos) | (DISABLE << MPU_RASR_B_Pos) | (x << MPU_RASR_S_Pos))

And in src\ASF\sam\boards\same70_xplained\init.c replace CONF_BOARD_ENABLE_CACHE_AT_INIT with CONF_BOARD_ENABLE_CACHE.

With these DCache is enabled but USB uses non-cacheable buffer and works reliably!

All above I tried with the (not so) old ASF 3.38 example. But I also tried the "USB Host Vendor" example from the new ASF4 (aka Atmel START: http://start.atmel.com) but there no more DCache at all (searching for SCB_Invalidate or SCB_Clean and no usage except their definitions from \CMSIS\Include\core_cm7.h). This complete avoidance of cache as well as the silence from the mentioned bugzilla entry could indicate some known but not yet public HW trouble in SAME70 (at least revision A)?

At least couldn't see anything in errata related to USB/DMA/DCACHE... I ordered few E70 revision B free samples and if they'll arrive our HW engineer will solder on the evaluation board but I doubt it will change anything.