SAME70 Timer Counter 2-bit Gray Counter

Go To Last Post
3 posts / 0 new
Author
Message
#1
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

 

Hello All,

 

I am trying to generate 2-bit gray code as described in section 48.6.17 of the SAM E70 datasheet. I am using the SAM E70 Xplained evaluation kit. I have been partially sucessful in doing this, since I can see the appropriately generated waveform on the TIOA2 output. The problem is that I don't see the corressponding signal on the TIOB2 output, which is permanently left at logic level 1.

 

I have tried a different set of outputs (TIOA0 and TIOB0), but the result is the same. I have also checked the setting of the GCEN bit of the TC_SMMR register, which is correctly set with a value of one. I assume I have missed sonmething in the initialisation, but the documentation is a bit sparse and I don't know where to go from here.

 

Here is my initialisation code (derived from TC waveform example):

 

 


    #define TC_CHANNEL_WAVEFORM		2

    uint32_t ra, rc;

    /** Configure PIO Pins for TC */
    ioport_set_pin_mode(PIO_PA26_IDX, IOPORT_MODE_MUX_B);
    /** Disable I/O to enable peripheral mode) */
    ioport_disable_pin(PIO_PA26_IDX);

    /** Configure PIO Pins for TC */
    ioport_set_pin_mode(PIO_PA27_IDX, IOPORT_MODE_MUX_B);
    /** Disable I/O to enable peripheral mode) */
    ioport_disable_pin(PIO_PA27_IDX);

    /* Configure the PMC to enable the TC module. */
    sysclk_enable_peripheral_clock(ID_TC2);

    /* Init TC to waveform mode. */
    tc_init(TC0, TC_CHANNEL_WAVEFORM,
    /* Waveform Clock Selection */
    gc_waveconfig[gs_uc_configuration].ul_intclock
    | TC_CMR_WAVE /* Waveform mode is enabled */
    | TC_CMR_ACPA_SET /* RA Compare Effect: set */
    | TC_CMR_ACPC_CLEAR /* RC Compare Effect: clear */
    | TC_CMR_CPCTRG /* UP mode with automatic trigger on RC Compare */
    );

    tc_set_writeprotect(TC0, 0);

    tc_init_2bit_gray(TC0, TC_CHANNEL_WAVEFORM, TC_SMMR_GCEN);

    /* Configure waveform frequency and duty cycle. */
    rc = (sysclk_get_peripheral_bus_hz(TC0) /
    divisors[gc_waveconfig[gs_uc_configuration].ul_intclock]) /
    gc_waveconfig[gs_uc_configuration].us_frequency;
    tc_write_rc(TC0, TC_CHANNEL_WAVEFORM, rc);
    ra = (100 - gc_waveconfig[gs_uc_configuration].us_dutycycle) * rc / 100;
    tc_write_ra(TC0, TC_CHANNEL_WAVEFORM, ra);

    /* Enable TC TC_CHANNEL_WAVEFORM. */
    tc_start(TC0, TC_CHANNEL_WAVEFORM);

 

 

Thank you for any assistance offered.

 

Kind regards,

 

 

Peter

 

 

 

 

 

 

This topic has a solution.
Last Edited: Tue. May 22, 2018 - 08:17 AM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Take a closer look at the tc_init() function parameters which eventually setup the channel mode register (TC_CMR).  I don't see any reference to TC_CMR_BCPB_SET or TC_CMR_BCPB_CLEAR.  Refer to section 48.7.3 in the datasheet BCPB:RB Compare Effect on TIOB (bits 25:24), and BCPC: TC Compare Effect on TIOB (bits 27:26).

This reply has been marked as the solution. 
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

 

Thanks for the suggestion. I have now found the source of the problem.

 

The setting of the EEVT field in the TC_CMR register was incorrect. I had assumed that this field would be ignored if the EEVTEDG field was set to NONE. It is not ignored and the value of 0 defined TIOB as an input not an output, so not surprising that no signal was observed at the pin.