SAMC21, different VDDIOs so i don't need level translators?

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Hi.

Developing a board using an ATSAMC21.

The datasheet table 7-5 lists GPIO Clusters, each refer to a specific VDDIO. Does this mean that part of the IOs can be at 5V Supply, another part at 3V3?

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You'll need to get confirmation from Atmel as to whether that's advisable. Generally they expect that all power pins are tied together. For example in the SAMD21, which also has GPIO clusters, the datasheet also states that "the same voltage must be applied to both VDDIN , VDDIO and VDDANA. This common voltage is referred to as VDD in datasheet." under section titled Power Supply Considerations.

 

Andrew

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Hi andrew, thanks for answering.

The SAM C21 is different, it is actually designed to have different IO voltage than core/analog. I guess they figured it would be nicer to further separate the analog and digital domain (also because you can have different power domains between analog and logic, analog at 5V, logic at 3v3 for example)

 

over at the eevblog forum some users tested and confirmed that what i asked is not possible, there is some 8 ohm resistance measured between the various VDDIO so they are effectively tied together.

The referral to the different clusters is probably related to better determine the current path.

Infact, this is the case for probably any mcu i've seen. different VDD are used to power different parts of the chip. In any case there is a reference in the datasheet "all vdd pin must be connected at the same potential" or something like that. Since this explicit reference was missing in the SAMC21, while there were references on VDDANA, VDDCORE and VDDIN i hoped that different domains within ports was possible.

 

Sure it would have helped me as i could skip adding level translation for some pin.. not for cost reasons but rather for lack of real estate

this is present on FPGAs by the way.. it's not some crazy delusion i had :)

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JPortici wrote:
The SAM C21 is different, it is actually designed to have different IO voltage than core/analog.

Yes, that is the case - see the datasheet:

Atmel-42364J-SAM-C20_Datasheet_Complete-11/2016 wrote:

8.2. Power Supply Considerations
8.2.1. Power Supplies

The SAM C20 has several different power supply pins:
• VDDIO: Powers I/O lines and XOSC. Voltage is 2.70V to 5.50V.
• VDDIN: Powers I/O lines and the OSC48M, TOSC and internal regulator. Voltage is 2.70V to 5.50V.
• VDDANA: Powers I/O lines and the ADC, AC, PTC, OSCULP32K, OSC32K and XOSC32K.
Voltage is 2.70V to 5.50V.
• VDDCORE: Internal regulated voltage output. Powers the core, memories, peripherals, and
FDPLL96M. Voltage is 1.2V typical.
The same voltage must be applied to both VDDIN and VDDANA. This common voltage is referred to as
VDD in the datasheet. VDDIO must always be less than or equal to VDDIN. 

and:

8.2.3. Typical Powering Schematics

The SAM C20 uses a single supply from 2.70V to 5.50V or dual supply mode where VDDIO is supplied
separately from VDDIN.

 

It is not uncommon these days for chips to have such an arrangement; eg, core at 1,8V and IO at 3V.

 

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andrewjfox wrote:
Generally they expect that all power pins are tied together.

Not in this case - see above.

For example in the SAMD21,

The D21 is an older part.

The L21 can also have different IO and "main supply" voltages - and adds the further option of a battery backup supply!

 

It is all clearly stated in the datasheets.

 

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but what is not clearly stated is if different IO blocks can be powered at different voltage levels. Measuring resistance between the various VDDIO pins suggests that it's not possible.

And i don't have a sacrifical mcu to test it. And i wouldn't even trust it to be in a product, if i don't have o document (datasheet) guaranteeing it can be done.

Actually, one IO block is powered by VDDANA. Maybe i can move the 5V functions there and power the rest of the logic at 3V3 (mostly CAN and UART)

That should work, right?

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In this case, the question is whether the separate Vddio pins (up to 3 in the 64pin package) can have separate supply voltages, since they're associated with separate "GPIO Clusters", and it might be desirable to drive 3.3V logic with one cluster and 5V logic with a different cluster.

And the answer is still no - all of the Vddio (AND Vddana too) need to be at the same voltage.

 

 

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westfw wrote:
In this case, the question is whether the separate Vddio pins (up to 3 in the 64pin package) can have separate supply voltages

Good point.

That one is not explicitly stated in the datasheet, but it does always and only refer to "VDDIO" as a single supply.

The Scematic Checklist section says,

45.3. Power Supply
The SAM C20 supports a single power supply or dual power supplies from 2.7 to 5.5V.

Which further suggests that there is just one "VDDIO".

 

it might be desirable to drive 3.3V logic with one cluster and 5V logic with a different cluster.

Indeed - they have missed an opportunity here!

 

all of the Vddio (AND Vddana too) need to be at the same voltage.

No: VDDIO can be different from VDDANA - but VDDANA must be the same as VDDIN

 

The same voltage must be applied to both VDDIN and VDDANA. This common voltage is referred to as
VDD in the datasheet. VDDIO must always be less than or equal to VDDIN.

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Sorry for resurrecting an old thread, but it comes up on Google when looking for this stuff.

 

The various GPIO clusters allow you to have different clusters at different voltage levels. There are two available, VDDIN and VDDIO/VDDANA. I'll just mention VDDIO from now on because VDDANA must be the same as it.

 

For example, on the 32 pin C1:

 

VDDIN - PA27/28/30/31

VDDIO - All others

 

VDDIO must be <= VDDIN. This is rather unfortunate because it means that you can only ever have 4 higher voltage pins.

 

In my case I wanted a lot of 5V GPIOs and a 3.3V UART, but it's impossible. The most you can get is 6 GPIOs on VDDIN with a 64 pin device, with a limited selection of peripherals.