Hi guys, got any idea like what will be the maximum SPI clock speed in Atmel SAM E70?
Silly beans are always silly
in page 931, section 126.96.36.199 Clock Generation
It says that the SPI clock is generated by dividing peripheral clock between value 1 and 255.
If that is so, then if my peripheral clock is 300MHz, then the SPI clock can vary between 300MHz to 1.17MHz.
Am I right?
The maximum peripheral clock is 150 MHz.
i think it should be something like this:
188.8.131.52 SPI Characteristics
Master Write Mode
maximum pad speed (see Section 184.108.40.206 “I/O Characteristics”)
SPI0_SPCK - PD22 - GPIO_AD
SPI1_SPCK - PC24 - GPIO_AD
Pin Group 3 = GPIO_AD
Pin Group3(3) Maximum output frequency
Drive Level High: 75MHz
Drive Level Low: 50MHz
Master Read Mode
For a non-volatile memory with tvalid (or tv) = 5 ns, fSPCKmax = 63 MHz at VDDIO = 3.3V.
So, yes, with 300MHz core clock, the peripheral clock can have a max of 150MHz.
You are right.
Now am feeling pretty confused.
Max. CoreClock with 300MHz is fine
From there you get max. Peripheral Clock 150MHz
The internal SPI part can operate with peripheral clock
so far so good. but that does not mean you necessarily get that frequenzy out onto the actual pin.
You still have to consider the (see datasheet) 56. Electrical Characteristics -> 56.14 Timings for STH Conditions -> 220.127.116.11 SPI Characteristics
as well as 56.13 Timings for Worst-Case Conditions -> 18.104.22.168 SPI Characteristics
in there you get equatios to consider.
And as a rough estimate: you got the 22.214.171.124 IO Characteristics -> in there you have max. freq. for pin_group types. when looking at the SPI pin e.g. SPI0_SPCK which is on 144pin package at PD22 which is in pin_group GPIO_AD you get what i wrote
its pretty clear,
E70tryhard seems like a good title.
Thanks a lot.
Again, if you have any experience in USB or external flash, then you can help me.
I got stuck on few things.
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