I am following Atmel document AT09002, Section 1.2 in attempt to put the SAMG55 device into Bootloader mode.
I have verified on my oscilloscope that I am strobing the NRST signal appropriately, but my NCHG signal will always stay high, never going low.
AT09002 indicates NRST should be taken low for minimum 1ms, and high for minimum 50ms.
This conflicts with the SAMG55 datasheet (indicates the NRST high time should be less than 50ms, and NRST low time greater than 1us)
In any event, if I try both timings (NRST taken high for 55ms and 25ms respectively), but NCHG will still remain high after the 10 NRST low sequences.
Any other thoughts on how to enter Bootloader mode ?
AT09002 indicates toggle ten times in a row, without communicating via I2C or SPI bus between resets.
I have verified that SPI select signal NSS remains high, there are no SPI clock transitions, nor is there any I2C clock transitions.
Another Atmel document indicates for SAMG55 ...
Security bit (GPNVM bit 0) • Boot from bootloader disabled. Boot from flash only.
I presume this means the Bit 0, should be cleared. Via EDBG, I read GPNVMBITS = 0x02, which indicates BOOT_MODE = 1.
This seems to be OK.
AT09002 Section 1.2.1 indicates Bootloader mode after the "force bootloader sequence" detection indicates a "bootloader reset counter" of 10 times.
The application is able to clear the "bootloader reset counter", which exists at start of RAM at 0x20000000
I have verified my application is not writing to this address ...
I was concerned possibly my app might have been clearing the "bootloader reset counter" immediately upon NRST being taken high
Mind you, AT09002 is quite unclear here.
The bootloader reset counter is located at the first address of the device SRAM and its clear value is: 0x00DA1981.
What does this exactly mean ? Do I write that value to 0x20000000 to clear the "bootloader reset counter" ?
Any help is appreciated.